In 2012, Sony developed a next-generation back-illuminated CMOS image sensor which “embodies the continuous evolution of the camera.”
This next-generation image sensor layers the pixel section containing formations of back-illuminated structure pixels onto chips containing the circuit section for signal processing, which is in place of supporting substrates for conventional back-illuminated CMOS image sensors.
Sony has succeeded in establishing a structure that layers the pixel section containing formations of back-illuminated structure pixels over the chip affixed with mounted circuits for signal processing, which is in place of supporting substrates used for conventional back-illuminated CMOS image sensors. By this stacked structure, large-scale circuits can now be mounted keeping small chip size. Furthermore, as the pixel section and circuit section are formed as independent chips, a manufacturing process can be adopted, enabling the pixel section to be specialized for higher image quality while the circuit section can be specialized for higher functionality, thus simultaneously achieving higher image quality, superior functionality and a more compact size. In addition, faster signal processing and lower power consumption can also be achieved through the use of leading process for the chip containing the circuits.
Features of stacked CMOS image sensor
- Large-scale signal processing circuits required for higher image quality and better functionality are built-in.
- More compact image sensor chip size.
- Even higher image quality of the pixel section by adopting manufacturing processes specialized for superior image quality.
- Faster speeds and lower power consumption by adopting the leading process for the circuit section.
Stacked CMOS image sensors deliver “superior image quality and advanced functionality in a compact size.“
This is an update to the previous blog, New Sony Exmor RS IMX230 for Smartphone Photography: Industry’s First Stacked CMOS Image Sensor with an Image Plane Phase Detection Signal Processing Function for High-Speed AF.
Sony has set a goal to develop a “Super Reality” sensor that surpasses human vision to achieve high speeds and high picture quality as depicted in this diagram here.
Sony will augment production facilities used in the mastering processes and layering and futher downstream processes*2 for stacked CMOS image sensors at Sony Semiconductor’s Nagasaki Technology Center (“Nagasaki TEC”) and Yamagata Technology Center (“Yamagata TEC”) in 2016.
April 07, 2015
Sony Further Increases Production Capacity for Stacked CMOS Image Sensors
– Sony bolsters total production capacity for image sensors to approximately 87,000 wafers per month, in order to reinforce its supply capability for smartphones –
Sony Corporation (“Sony”) announces that it plans to further invest in Sony Semiconductor Corporation (“Sony Semiconductor”) in the fiscal year ending March 31, 2016 (“FY15”) in order to increase its production capacity for stacked CMOS image sensors*1.
This investment is intended primarily to augment production facilities used in the mastering processes and layering and futher downstream processes*2 for stacked CMOS image sensors at Sony Semiconductor’s Nagasaki Technology Center (“Nagasaki TEC”) and Yamagata Technology Center (“Yamagata TEC”).
With investments such as the one announced in February*3 and this supplementary investment, Sony plans to increase total production capacity for image sensors from the current level of approximately 60,000 wafers per month to the level of approximately 87,000 wafers per month*4 by the end of September 2016. The total additional investment amount is projected to be approximately 45 billion yen, comprising approximately 24 billion yen of investments in Nagasaki TEC and approximately 21 billion yen of investments in Yamagata TEC.
Stacked CMOS image sensors deliver superior image quality and advanced functionality in a compact size. Demand for these image sensors is anticipated to further increase, particularly within the expanding market for mobile devices such as smartphones and tablets. Sony is striving to bolster its production capacity for stacked CMOS image sensors in order to solidify its leading position in the image sensor market.
*1:CMOS image sensors in a stacked structure that layer the pixel section containing back-illuminated structure pixels onto semiconductor chips containing the circuit for signal processing, in contrast to the supporting substrates used in conventional back-illuminated CMOS image sensors.
*2:The mastering process refers to the manufacture of photodiodes and wiring processes for stacked CMOS image sensors. The layering process refers to the layering of semiconductor chips containing back-illuminated structure pixels on top of semiconductor chips containing the circuit for signal processing.
*3:A separate investment of approximately 105 billion yen, intended to bolster production capacity from the current level of approximately 60,000 wafers per month to the level of approximately 80,000 wafers per month by the end of June 2016, was previously announced on February 2, 2015.
*4:This total production capacity (300mm wafer basis) includes the output of foundry operations to which Sony outsources a part of the manufacturing process. For the purposes of calculating total production capacity, the capacity of 200mm wafer production lines at the Kagoshima Technology Center and Nagasaki TEC are converted into equivalent amounts in terms of 300mm wafer production.
Overview of Investment
- To bolster production capacity in order to meet growing demand for stacked CMOS image sensors
- Sony Semiconductor Corporation
Nagasaki TEC (Isahaya City, Nagasaki Prefecture), Yamagata TEC (Tsuruoka City, Yamagata Prefecture)
- Augment production facilities for stacked CMOS image sensors (mastering, processes, and layering and further downstream processes)
- Approximately 45 billion yen (projected)
Approximately 24 billion yen for Nagasaki TEC; Approximately 21 billion yen for Yamagata TEC